Field of the Invention
The invention relates to a method for manufacturing, by self alignment, the doped zones of an MOS component. It finds its application in the manufacture of MOS and BIPMOS products, also called IGT, COMFET, GEMFET, with polycrystalline silicon gate designated under the name of polysilicon. It applies more particularly to manufacture using the VD MOS (Vertical metal oxide semiconductor) technology.
A DMOS type component is formed by cells or strips where the source contacts are taken and by gate zones formed of oxide and polysilicon. In the cells, it is necessary to introduce impurities:
of type P which will determine the parameters of the channel, PA1 N+, which will determine the source parameters, PA1 P+: which will contribute to obtaining good characteristics of: ohmic contact with the aluminum connection, PA1 in forming two protecting studs on each side of a first zone to be doped, PA1 in carrying out doping of a first type with high concentration in the first zone to be doped, PA1 in oxidizing the assembly so that the protecting studs are much less oxidized than the rest, PA1 in cleaning this oxide as well as the studs defining the window whose relative heights are such that the studs disappear completely during the procedure, PA1 in carrying out doping of a second type of the silicon at the level of the two openings released by disappearance of the studs. PA1 1--washing PA1 2--implantation (the oxide forms a screen) PA1 3--annealing
voltage resistance, PA2 resistance Rb of the parasite lateral NPN transistor.
The N+ and P+ impurities are limited by the polysilicon. It is the different anealing operations which determine the length and doping of the channel. These two parameters are thus the same for all the cells which form the MOS.